The higher the data transfer rate in the channel C is, the sooner the timing accuracy during any decision-making process gets a key issue in the design of high-speed serial links. Such decisions have to be made at several points in the system, for example when launching a bit at the transmitter, when determining the bit value of an incoming symbol at the receiver, and when measuring the position of the bit edge at the receiver to determine if the bit is early or late. Any inaccuracy or noise in the timing of those decisions is directly degrading the jitter budget of the link and therefore severely complicating the design.
The invention relates to the calibration of the relative timing positions of sampling phases. High accuracy of the sampling clocks is a key requirement in the design of high-speed serial links above 4 GBit/s in high performance CMOS (complementary metal oxide semiconductor) processes. If there is any offset in the position of the individual sampling edges, timing jitter is added to the system. At 100 ps to 200 ps cycle time, a few picoseconds are already making the difference between an acceptable and an unacceptable bit error rate (BER).
One reason for an offset which leads to inaccuracy in the sampling phase lies in the manufacturing process. The gate thickness for deep-sub-micron CMOS technologies measures only a couple of atoms. The threshold voltage of a CMOS device is a function of the gate thickness. Due to the fact that the number of atomic layers that form the gate oxide is very difficult to control, threshold voltage shifts have to be expected, which in turn lead to aforementioned inaccuracies.
One possibility to reduce the inaccuracy is to increase the power. Another possibility consists in there that the circuit layout with regard to the clock distribution is done very carefully. But both solutions are not always desirable and have obviously disadvantages.